I. Field of the Disclosure
The technology of the disclosure relates generally to monolithic three dimensional (3D) integrated circuits (ICs) (3DICs).
II. Background
Mobile communication devices have become common in contemporary society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements of mobile devices and generates a need for more powerful batteries. Within the limited space of the housing of a mobile communication device, batteries compete with the processing circuitry. The limited space contributes pressure to a continued miniaturization of components and power consumption within the circuitry. While miniaturization has been of particular concern in the integrated circuits (ICs) of mobile communication devices, efforts at miniaturization of ICs in other devices have also proceeded.
Historically, elements within an IC have all been placed in a single two dimensional (2D) active layer with elements interconnected through one or more metal layers that are also within the IC. Efforts to miniaturize are reaching their limits in a 2D space and thus, design thoughts have moved to three dimensions. While there have been previous efforts to connect two or more ICs through a separate set of metal layers outside the IC proper, that solution is not a properly three dimensional (3D) approach. In past efforts, two ICs have been stacked one atop another with connections made between the two ICs through solder bumps (i.e., the so called “flip chip” format). Likewise, there are system in package (SIP) solutions that stack ICs atop one another with connections made between the chips with Through Silicon Vias (TSVs). More specifically, TSVs allow vertical stacking of multiple dies that are individually fabricated. However, the quality of TSV-based 3DICs strongly depends on the TSV dimensions and parasitics, which are limited to memory-on-logic or large logic-on-logic designs with a relatively small number of die-to-die interconnects. Further, while the flip chip and TSV embodiments arguably represent 3D solutions, the amount of space required to effectuate a flip chip remains large. Likewise, the space required to implement a TSV relative to the overall size of the chip becomes space prohibitive.
In response to the difficulties in effectuating small ICs that meet miniaturization goals, industry has introduced monolithic 3DICs. Monolithic 3DICs offer vertical stacking of devices (including logic circuits) on a single die, with the potential to significantly reduce die area and increase die performance. More specifically, monolithic 3DICs involve building electronic components and their connections within multiple tiers on a single die. Connections between the tiers within the die are made with Monolithic Inter-tier Vias (MIVs). Such MIVs are much smaller in size than the previously described TSVs, thus allowing 3DICs using MIVs to achieve an integration density that is orders of magnitude higher than 3DICs employing TSVs.
Although monolithic 3DICs have the potential to reduce die area while increasing die performance, current monolithic 3DIC design methodologies are limited to modified versions of 2D block-level integration. More specifically, commercial 2D place and route (P&R) tool flows customized for 3DICs are employed for 3D P&R processes. Using existing 2D P&R tools with 3DIC customizations in this manner places MIVs throughout otherwise usable whitespace within a layout design. This scattered placement of MIVs can result in inefficient occupation of otherwise usable whitespace within the monolithic 3DIC. Such inefficient use of the whitespace in a monolithic 3DIC can prevent the 3DIC from maximizing achievable performance. More specifically, inefficient use of the whitespace can impair optimized use of other components, such as, for example, buffer insertion used to achieve timing optimization. Thus, it would be advantageous to design monolithic 3DICs in a manner that more efficiently uses the whitespace in the 3DIC so as optimize the use of other components within the 3DIC.